Xilinx Coregen and EDK

 Adding Xilinx Coregen macros to EDK designs

1. Generate coregen macro, enable generation of .v files. The netlist will be a .ngc file

2. Look at .v file, will have a synthesis translate_off  and on directive around the behavioral simulation model

3. Synthesis will take any module with an io port definition and treat it as a blackbox.

   eg black box definition:

             module foo ( clk , rst, datain, dataout) ;

                input clk, rst;

                input datain ;

                output dataout;

             //If you want to include behavioral simulation code here 

             //do so within synthesis translate off and on

             // XST and synplicity should recognize this

             //synthesis translate_offf

              ....

              ....

              ....

             //synthesis translate_on

 

             endmodule

4. Synthesize using XST. This will create an .ngc file

5. In pcores/<ip_name>/data directory create a .bbd file

          This is just a comma separated list of the coregen.ngc files

          eg: cam_v6_1.ngc, srlfifo39.ngc

6. In the .mpd file add

          OPTION STYLE = MIX

          OPTION RUN_NGCBUILD = TRUE

7. Create pcores/<ip_name>/netlist directory and copy the .ngc files listed in step (5) here.

8. Invoke EDK build flow.