1. Generate pcore, enable the generate in verilog option
2. This will create
user_logic.v
3. Create a
synplify project file for user_logic.v and all modules underneath it.
4. In synplify go
to File->New, then select new project file.
5. Add user_logic.v
and other modules referenced by it. Synplify will also treat modules with only
IO declaration as a blackbox. These blackbox modules will be
resolved in the ngcbuild step.
6. Go under
implementation options, select the right xilinx part no.
7. Most important
under implementation options, disable automatic IO insertion.
8. Run in synplify
9. Synplify
generates an .edf file
10. Copy to
pcores<ip_name>/netlist directory and run edif2ngd user_logic.edf, rename
output from user_logic.ngo to user_logic.ngc.
11. In
pcores/hdl/verilog, edit user_logic.v to remove all code between the IO
declaration and endmodule. Synthesis will take any module with an io port
definition and treat it as a blackbox.
eg black box definition:
module foo ( clk , rst, datain,
dataout) ;
input clk, rst;
input datain ;
output dataout;
//If you want to include behavioral
simulation code here
//do so within synthesis translate off
and on
// XST and synplicity should recognize
this
//synthesis translate_offf
....
....
....
//synthesis translate_on
endmodule
12. Edit the
pcores/<ip_name>/data/.pao file , if need be , it should only
reference user_logic.v (in addition to the the other edk libraries and vhdl
wrapper).
13. In
pcores/<ip_name>/data directory create a .bbd file
This is just a comma separated list of
the coregen.ngc files, with a first line saying Files
eg bbd file:
# This is a comment, must have Files
keyword below
Files
srlfifo39.ngc , user_logic.ngc
14. In the .mpd
file add
OPTION STYLE = MIX
OPTION RUN_NGCBUILD = TRUE
15. Invoke EDK
build flow.
16. If it fails MAP
, it could be because synplify has not optimized away unconnected inputs. Create dummy connection to the problem
LUTs. Rerun synplify.
17. Complete build.
This has been
tested on the sample ml509_dpi design with fifo read logic.
It ran into a
problem with MAP. Issue was traced to the Intr_Event not being driven, drove it
with a dummy register and then it worked.
(should try a
simply tie off and see)
Sample synplify
project file:
#-- Synplicity,
Inc.
#-- Version
C-2009.06-SP1
#-- Written on Wed
Apr 14 12:30:27 2010
#project files
add_file -verilog
"./srlfifo39.v"
add_file -verilog
"./tag_data_splitter.v"
add_file -verilog
"./tag_parser.v"
add_file -verilog
"./user_logic.v"
#implementation:
"rev_1"
impl -add rev_1
-type fpga
#device options
set_option
-technology Virtex5
set_option -part
XC5VLX110T
set_option -package
FF1136
set_option
-speed_grade -1
set_option
-part_companion ""
#compilation/mapping
options
set_option
-use_fsm_explorer 0
set_option
-top_module "user_logic"
#
sequential_optimization_options
set_option
-symbolic_fsm_compiler 1
# Compiler Options
set_option
-compiler_compatible 0
set_option
-resource_sharing 1
# mapper_options
set_option
-frequency auto
set_option
-write_verilog 0
set_option
-write_vhdl 0
# Xilinx Virtex2
set_option
-run_prop_extract 1
set_option -maxfan
10000
set_option
-disable_io_insertion 1
set_option -pipe 1
set_option
-update_models_cp 0
set_option
-retiming 0
set_option
-no_sequential_opt 0
set_option
-fixgatedclocks 3
set_option
-fixgeneratedclocks 3
# Xilinx Virtex5
set_option
-enable_prepacking 1
#VIF options
set_option
-write_vif 1
#automatic place
and route (vendor) options
set_option
-write_apr_constraint 1
#set result
format/file last
project
-result_file "./rev_1/user_logic.edf"
#
#implementation
attributes
set_option
-vlog_std v2001
set_option
-project_relative_includes 1
impl -active
"rev_1"
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