Friday, November 2, 2012

Xilinx commands and Filetypes

Xilinx commands and filetypes One-pager

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Xilinx File Types 

.ngc : Netlist file


.ngo : Similar to .ngc, output of Coregen, EDIF2NGD
 

.ncd : Mapped, placed , routed file
 

.ucf : User constraint file, read by NGDBUILD .
 

.pcf : Physical constraints file, output by MAP and used by PAR.

 
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NGCBUILD: Merges multiple .ngc (synthesized netlist files) into a single .ngc file. Useful for chipscope core insertion.

syntax:

ngcbuild -i <top_level_input_file>.ngc  <output_file>.ngc  

Options:

-sd : specify source directories? if all .ngc files not in the same directory as <top_level_input_file>.ngc

 
NGDBUILD: Reads (multiple) .ngc files to create and single .ngd file. This file is the entry point for MAP,PAR.
 

MAP: Reads .ngd file, output mapped .ncd file and optionally .pcf files.
 

PAR: Place and route, reads mapped .ncd file and outputs routed .ncd file

 
TRCE: Trace, reads .ncd file and what else.

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Chipscope Core Inserter

Once you have .cdc file, can run inserter from the command line.

syntax:

inserter -insert <file.cdc> <input_file>.ngc <output_file>.ngc

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Example windows script:
 
rem Clean up the results directory

rmdir /S /Q results

mkdir results

echo 'Synthesizing HDL example design with XST';

xst -ifn xst.scr

move xilinx_pci_exp_ep.ngc .\results\endpoint_blk_plus_v1_9_top.ngc

cd results

echo 'Running ngdbuild'

rem   ngdbuild -verbose -uc ..\xilinx_pci_exp_blk_plus_1_lane_ep_xc5vlx50t-ff1136-1.ucf endpoint_blk_plus_v1_9_top.ngc -sd ..\..\..\..\..\

ngdbuild -verbose -uc ..\xupv5-lx110t_pcie_x1_plus.ucf endpoint_blk_plus_v1_9_top.ngc -sd ..\..\..\..\
 

echo 'Running map'

map -timing -ol high -xe c -pr b -o mapped.ncd endpoint_blk_plus_v1_9_top.ngd mapped.pcf

echo 'Running par'

par -ol high -xe c -w mapped.ncd routed.ncd mapped.pcf

echo 'Running trce'

trce -u -v 100 routed.ncd mapped.pcf

echo 'Running design through netgen'

netgen -sim -ofmt verilog -ne -w -tm xilinx_pci_exp_ep -sdf_path ..\..\implement\results routed.ncd 

echo 'Running design through bitgen'

bitgen -w routed.ncd

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command to create ace file.

impact -batch pcie_ace.cmd

pcie_ace.cmd >>

setMode -acecf

addCollection -name "ML509"

addDesign -version 6 -name "cfg4"

addDeviceChain -index 0

setCurrentDesign -version 6

setCurrentDeviceChain -index 0

addDevice -p 1 -file "./pcie_dma_top.bit"

generate -active ML509

quit

<< 

From xapp859 for ml505

bitgen -g ConfigRate:20 <file>

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